`timescale 1ns / 1ps

module ID_EX(
    input clk,
    input reset,
    input stall,
    input [31:0] D_V1,
    input [31:0] D_V2,
    input [31:0] D_imm32,
    input [31:0] D_PC,
    input [2:0] D_RinSel,
    input D_RegWr,
    input [3:0] D_Aop,
    input D_ASrc,
    input D_MemWr,
    input [4:0] D_A1,
    input [4:0] D_A2,
    input [1:0] D_Tu1,
    input [1:0] D_Tu2,
    input [4:0] D_A3,
    input [1:0] D_Tn,
    input [1:0] D_store,
    input [2:0] D_Dop,
    input D_start,
    input [1:0] D_Mop,
    input D_HLWr,
    input D_MDDst,
    input D_HLSrc,
    input D_shmt,
    input [4:0] D_shamt,
    input D_ld,
    input D_st,
    input [31:0] D_instr,
    input D_CP0Wr,
    input D_eret,
    input D_isBD,
    output reg [31:0] E_V1,
    output reg [31:0] E_V2,
    output reg [31:0] E_imm32,
    output reg [31:0] E_PC,
    output reg [2:0] E_RinSel,
    output reg E_RegWr,
    output reg [3:0] E_Aop,
    output reg E_ASrc,
    output reg E_MemWr,
    output reg [4:0] E_A1,
    output reg [4:0] E_A2,
    output reg [1:0] E_Tu1,
    output reg [1:0] E_Tu2,
    output reg [4:0] E_A3,
    output reg [1:0] E_Tn,
    output reg [1:0] E_store,
    output reg [2:0] E_Dop,
    output reg E_start,
    output reg [1:0] E_Mop,
    output reg E_HLWr,
    output reg E_MDDst,
    output reg E_HLSrc,
    output reg E_shmt,
    output reg [4:0] E_shamt,
    output reg E_ld,
    output reg E_st,
    output reg [31:0] E_instr,
    output reg E_CP0Wr,
    output reg E_eret,
    output reg E_isBD
    );

    initial begin
        E_V1 <= 0;
        E_V2 <= 0;
        E_imm32 <= 0;
        E_PC <= 0;
        E_RinSel <= 0;
        E_RegWr <= 0;
        E_Aop <= 0;
        E_ASrc <= 0;
        E_MemWr <= 0;
        E_A1 <= 0;
        E_A2 <= 0;
        E_Tu1 <= 0;
        E_Tu2 <= 0;
        E_A3 <= 0;
        E_Tn <= 0;
        E_store <= 0;
        E_Dop <= 0;
        E_start <= 0;
        E_Mop <= 0;
        E_HLWr <= 0;
        E_MDDst <= 0;
        E_HLSrc <= 0;
        E_shmt <= 0;
        E_shamt <= 0;
        E_ld <= 0;
        E_st <= 0;
        E_instr <= 0;
        E_CP0Wr <= 0;
        E_eret <= 0;
        E_isBD <= 0;
    end

    always @(posedge clk) begin
        if(reset) begin
        E_V1 <= 0;
        E_V2 <= 0;
        E_imm32 <= 0;
    //    E_PC <= 0;
        E_RinSel <= 0;
        E_RegWr <= 0;
        E_Aop <= 0;
        E_ASrc <= 0;
        E_MemWr <= 0;
        E_A1 <= 0;
        E_A2 <= 0;
        E_Tu1 <= 0;
        E_Tu2 <= 0;
        E_A3 <= 0;
        E_Tn <= 0;
        E_store <= 0;
        E_Dop <= 0;
        E_start <= 0;
        E_Mop <= 0;
        E_HLWr <= 0;
        E_MDDst <= 0;
        E_HLSrc <= 0;
        E_shmt <= 0;
        E_shamt <= 0;
        E_ld <= 0;
        E_st <= 0;
        E_instr <= 0;
        E_CP0Wr <= 0;
        E_eret <= 0;
        E_isBD <= 0;
        end
        else if(stall)begin
        E_V1 <= 0;
        E_V2 <= 0;
        E_imm32 <= 0;
    //    E_PC <= 0;
        E_RinSel <= 0;
        E_RegWr <= 0;
        E_Aop <= 0;
        E_ASrc <= 0;
        E_MemWr <= 0;
        E_A1 <= 0;
        E_A2 <= 0;
        E_Tu1 <= 0;
        E_Tu2 <= 0;
        E_A3 <= 0;
        E_Tn <= 0;
        E_store <= 0;
        E_Dop <= 0;
        E_start <= 0;
        E_Mop <= 0;
        E_HLWr <= 0;
        E_MDDst <= 0;
        E_HLSrc <= 0;
        E_shmt <= 0;
        E_shamt <= 0;
        E_ld <= 0;
        E_st <= 0;
        E_instr <= 0;
        E_CP0Wr <= 0;
        E_eret <= 0;
    //    E_isBD <= 0;
        end
        else begin
            E_V1 <= D_V1;
            E_V2 <= D_V2;
            E_imm32 <= D_imm32;
            E_PC <= D_PC;
            E_RinSel <= D_RinSel;
            E_RegWr <= D_RegWr;
            E_Aop <= D_Aop;
            E_ASrc <= D_ASrc;
            E_MemWr <= D_MemWr;
            E_A1 <= D_A1;
            E_A2 <= D_A2;
            E_Tu1 <= D_Tu1;
            E_Tu2 <= D_Tu2;
            E_A3 <= D_A3;
            E_Tn <= D_Tn;
            E_store <= D_store;
            E_Dop <= D_Dop;
            E_start <= D_start;
            E_Mop <= D_Mop;
            E_HLWr <= D_HLWr;
            E_MDDst <= D_MDDst;
            E_HLSrc <= D_HLSrc;
            E_shmt <= D_shmt;
            E_shamt <= D_shamt;
            E_ld <= D_ld;
            E_st <= E_st;
            E_instr <= D_instr;
            E_CP0Wr <= D_CP0Wr;
            E_eret <= D_eret;
            E_isBD <= D_isBD;
        end
    end

endmodule
